In the early days of programmable devices, global clock signals or other global signals could be distributed using the general global routing resources of the device. Device sizes were small enough and desired speeds were low enough that skew was not a particular concern. However, as programmable devices became larger and desired speeds became higher, skew became a concern. One solution to the problem of global clock skew or other global signal skew was the development of a clock tree network commonly referred to as an “H-tree,” which allowed a clock signal or other global signals to be introduced at a single point on a device and be delivered to all points on the device with reduced skew.
However, as device sizes and speeds have continued to increase, the amount of metallization resources required to provide H-tree clock networks has increased dramatically and the margin for acceptable clock skew has decreased significantly. At the same time, the number of clocks and other signals to be distributed widely across a device also has increased dramatically. For example, devices frequently incorporate high-speed serial interfaces to accommodate high-speed signaling standards. Clocks derived from such interfaces using phase-locked loop (PLL), clock-data recovery (CDR), delay-locked loop (DLL), or dynamic phase alignment (DPA) techniques may have to be distributed throughout a device to wherever the associated data is being used or processed. Furthermore, many of these high-speed signaling standards involve multiple data streams, which may require multiple unique clock domains to be provided and consistently distributed throughout the device.